Project information
- Name: RISCV CPU [ Github Link ]
- Category: IAC coursework
- Location: Imperial College London, UK
Collaborative Endeavors: Crafting a Single-Cycle CPU and Advancing to Pipelining and Cache Memory.
Our team of four successfully engineered a single-cycle CPU from the ground up, featuring diverse instructions like addi, lw, and jal. This achievement led us to delve into pipelining, where we meticulously segmented tasks into Registers and Control Unit, Data Hazards, Control Hazards, and Testing. The culmination of our coursework involved the implementation of cache memory, encompassing both directly mapped and 2-way associative mapped approaches.