RISCV CPU
Project information:
- Category: Instruction-set Architecture and Compiler (IAC) coursework [Github link]
- Year: 2022
- Location: Imperial College London, London, UK
Our team of four successfully developed a single-cycle CPU from scratch using System Verilog and Verilator, featuring diverse instructions like addi, lw, and jal. This achievement led us to delve into pipelining, where we meticulously segmented tasks into Registers and Control Unit, Data Hazards, Control Hazards, and Testing. The culmination of our coursework involved the implementation of cache memory, encompassing both directly mapped and 2-way associative mapped approaches.
Block diagram of the RISCV single-cycle CPU
On the left, visualisation of the executed output of the CPU; Right, waveforms in gtkWave for debugging.